CMOS circuits of current semiconductor technology comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs. (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si having a (100) surface orientation.
It is known that electrons have a high mobility in Si with a (100) surface orientation and that holes have a high mobility in Si with a (110) surface orientation. In fact, hole mobility can be about 2.5 times higher on a 110-oriented Si wafer than on a standard 100-oriented Si wafer. It would therefore be desirable to create hybrid orientation substrates comprising 100-oriented Si (where nFETs would be formed) and 110-oriented Si (where pFETs would be formed).
Amorphization/templated recrystallization (ATR) is one prior art approach for providing such planar hybrid orientation substrates. FIGS. 1A–1C and 2A–2D outline examples of ATR methods described in U.S. application Ser. No. 10/725,850 for producing hybrid orientation silicon substrates. Specifically, FIGS. 1A–1C outline an ATR method for forming a bulk semiconductor hybrid orientation substrate. FIG. 1A shows starting substrate 10 comprising a first single crystal semiconductor substrate 20 having a first crystal orientation in direct contact with an upper second single crystal semiconductor layer 30 having a second crystal orientation different from the first. The interface 40, which is located between the semiconductor layers 20 and 30, is typically formed by a hydrophobic wafer bonding process. See, for example, Q. -Y. Tong and U. Gosele in Semiconductor Wafer Bonding, John Wiley, 1999.
FIG. 1B shows the structure of FIG. 1A being subjected to ion bombardment 50 in selected areas to create localized amorphized regions 60 extending from the top surface of semiconductor layer 30 to a depth ending in substrate layer 20 below interface 40. FIG. 1C shows the structure of FIG. 1B after localized amorphized regions 60 have been recrystallized (using semiconductor layer 20 as a template) to form single crystal semiconductor region 70 with the orientation of first semiconductor 20. Resulting substrate 80 now comprises two clearly defined single-crystal semiconductor regions with different surface orientations, i.e., non-amorphized regions 30′ of the second semiconductor and amorphized/recrystallized regions 70.
FIGS. 2A–2D outline an example of another prior art ATR method for producing a semiconductor-on-insulator (SOI) hybrid orientation substrate. FIG. 2A shows a starting substrate 90 comprising handle substrate 100, insulator layer 110, and a lower first single crystal semiconductor layer 120 having a first crystal orientation in direct contact with an upper second single crystal semiconductor layer 130 having a second crystal orientation different from the first. The interface 140 between semiconductor layers 130 and 120 is typically formed by a hydrophobic wafer bonding process.
FIG. 2B shows the structure of FIG. 2A being subjected to ion bombardment 150 in selected areas to create localized amorphized regions 160 extending from the top surface of insulator 110 up to a depth ending in semiconductor layer 130 above interface 140. FIG. 2C shows the structure of FIG. 2B after localized amorphized regions 160 have been recrystallized (using semiconductor layer 130 as a template) to form single crystal semiconductor region 170 with the orientation of upper semiconductor 130. Upper semiconductor layer 130 is then removed (by a process such as polishing and/or oxidation/wet etching) to produce substrate 180 of FIG. 2D. Substrate 180 comprises two clearly defined single-crystal semiconductor regions with different surface orientations, i.e., non-amorphized regions 120′ of the second semiconductor and amorphized/recrystallized regions 170, on buried insulator 110. Regions 170 and 120′ may be further thinned (again by processes such as polishing and/or oxidation/wet etching), if thinner semiconductor-on-insulators are desired.
It should be noted that the methods of FIGS. 1A–1C and 2A–2D do not show the additional steps that might be included to minimize the possibility of lateral templating. The sides of the region(s) 60 in FIG. 1B and 160 in FIG. 2B selected for amorphization and templated recrystallization would typically be at least partially isolated from adjacent crystalline regions by structures-such as trenches. The trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization. Trench formation would typically be effected by a process such as reactive ion etching (RIE) through a mask.
Like all ATR methods to date, the process flows of FIGS. 1A–1C and 2A–2D utilize the following sequence of steps to change the orientation of selected semiconductor regions from an original orientation to a desired orientation:                (a) forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer (or substrate) directly in contact with a second, upper (typically bonded) single crystal semiconductor layer, said first semiconductor having a first orientation and said second semiconductor having a second orientation different from the first;        (b) amorphizing one of the layers of the bilayer template stack in selected areas (by ion implantation through a mask, for example) to form localized amorphized regions; and        (c) recrystallizing the localized amorphized regions using the non-amorphized layer of the stack as a template, thereby changing the orientation of the semiconductor in the localized amorphized regions from its original orientation to a desired orientation.        
A potential problem with this way of implementing ATR is that the ion implant methods typically used for amorphization leave a damaged crystalline layer between the amorphized and the non-amorphized regions of the bilayer template stack. For the case of top amorphization and bottom templating (illustrated in the process flow of FIGS. 1A–1C), the damage layer is commonly referred to as an end-of-range (EOR) damage layer. This EOR damage layer interferes with the clean recrystallization of the amorphized region, both by introducing threading defects (that can propagate to the wafer's surface) and by leaving a band of dislocation loops at the position of the original damage layer. These various damaged regions and defects are illustrated in FIGS. 3A–3C. Specifically, FIG. 3A shows initial substrate 200 with bottom single crystal semiconductor layer 210 and top single crystal semiconductor layer 220 being subjected to an amorphizing ion implant 230. FIG. 3B shows the resulting amorphized region 240 and damaged crystalline region 250, and FIG. 3C shows the loops 260 and threads 270 remaining after a recrystallization anneal.
The amount of EOR damage depends somewhat on the ion implant conditions used for the amorphization. Typically, EOR damage can be reduced by implanting at low temperature (e.g., at liquid nitrogen temperature, 77K, rather than room temperature), by using heavier ions (e.g., Ge ions rather than Si ions), and with shallower implants. However EOR damage (or “beginning-of-range” damage for the case of top templating and bottom amorphization, when ion implantation is used to form a buried amorphous layer) is a characteristic of all ion implantation processes and is very difficult to avoid.
An additional difficulty with previous ATR methods of forming hybrid orientation substrates is that they require direct semiconductor-to-semiconductor (typically Si-to-Si) bonding. This is normally achieved with hydrophobic bonding, a bonding technique that is more difficult and less well developed than the more commonly used hydrophilic bonding. Hydrophobic (H-terminated) surfaces are more easily contaminated than hydrophilic ones, often leading to a choice to perform hydrophobic bonding in a vacuum environment. In addition, the widely used surface plasma treatments developed to allow room temperature bonding typically introduce surface oxygen, making them incompatible with an oxide-free bonded interface. Bonding at higher temperatures also can present difficulties, since most cleaving processes (used to separate the bonded layer from the wafer to which it was originally attached) are thermally activated and start occurring in the same temperature range as the bonding.
A new in-place bonding technique disclosed in U.S. application Ser. No. 10/978,551 provides an alternative route to the traditional direct Si-to-Si bonding described above. A basic embodiment of this technique is illustrated in FIGS. 4A–4E, which show the steps needed for forming Si mesas having a first orientation directly on a Si substrate having a second orientation. Specifically, FIG. 4A shows starting substrate 300 comprising lower single crystal semiconductor layer 310 having a first orientation, sacrificial spacer layer 320 (typically composed of SiO2), and upper single crystal semiconductor layer 330 having a second orientation different from the first. Upper semiconductor layer 330 is then patterned into island(s) 330′, as shown in FIG. 4B. In-place bonding between the semiconductor islands 330′ and the semiconductor substrate layer 310 is accomplished by gradually removing the spacer layer 320 in a wet etch solution that leaves the underside of semiconductor island 330′ and the top surface of the substrate layer 310 hydrophobic and strongly attracted to each other. As the spacer layer material 320 under island 330′ becomes more and more undercut (FIG. 4C), the island edges start to bond to the underlying semiconductor layer, as shown in FIG. 4D. The process is complete when the spacer layer is gone and the entire underside of each island is in direct contact with the underlying semiconductor substrates layer, as shown in FIG. 4E. However, hybrid orientation substrates formed by this technique have the drawback that they are inherently non-planar (since the semiconductor island 330′ is higher than the exposed regions of semiconductor 310 adjacent to the island).
While the basic process shown in FIGS. 4A–4E could, in principle, be modified and extended to achieve planar hybrid orientation substrates, these additional steps would come at the cost of substantial process complexity. FIGS. 5A–5I show one such example: a modification of the FIG. 4 process combined with a variation of a prior art epitaxial growth method described in U.S. application Ser. Nos. 10/696,634 and 10/250,241. FIG. 5A shows starting substrate 300 comprising lower single crystal semiconductor layer 310 having a first orientation, sacrificial spacer layer 320 (typically composed of SiO2), and upper single crystal semiconductor layer 330 having a second orientation different from the first. FIG. 5B shows upper semiconductor layer 330 after it has been patterned using hard mask structures 333 to produce semiconductor features 330′ and exposed regions 334 of sacrificial spacer 320. Hard mask features 333 are preferably formed from an insulating material such as SiO2 or silicon nitride. FIGS. 5C–5E show the progressive stages of in-place bonding that conclude when the entire undersides of semiconductor structures 330′ are in direct contact with semiconductor layer 310, as shown in FIG. 5E. FIG. 5F shows the structure of FIG. 5E after formation of insulating sidewall spacers 335, preferably composed of a material such as SiO2 or silicon nitride. Cavity 336 between sidewall spacers 335 is then filled and slightly overfilled with single crystal semiconductor 337, grown by a selective epitaxial growth process (templating from the bottom of cavity 336), as shown in FIG. 5G. Semiconductor material 337 is then planarized by a process such as CMP to produce the structure of FIG. 5H where reference numeral 338 refers to the planarized semiconductor material derived from layer 337. The structure of FIG. 5H is then further planarized to form the planar hybrid orientation structure 339 of FIG. 51.
In view of the difficulties and limitations described above, there is still a need for providing planar hybrid orientation substrates by ATR methods which (i) exploit the benefits of in-place bonding techniques, and (ii) avoid or minimize the formation of a crystalline damaged layer during the amorphization step, thereby allowing the formation of lower-defectivity hybrid orientation substrates.